The present subject matter generally concerns multi-layer and cascade capacitors for use in a range of frequency applications including high frequency applications, and more particularly concerns multiple capacitor components provided in monolithic packages. The present subject matter utilizes interconnect and attachment features to create devices with improved and/or idealized performance characteristics, including high capacitance, low equivalent series inductance (ESL), and low or tunable equivalent series resistance (ESR).
The diversity of modern technical applications creates a need for efficient electronic components and integrated circuits for use therein. Capacitors are a fundamental component used for filtering, decoupling, bypassing and other aspects of such modern applications which may include wireless communications, alarm systems, radar systems, circuit switching, matching networks, and many other applications. A dramatic increase in the speed and packing density of integrated circuits requires advancements in decoupling capacitor technology in particular. When high-capacitance decoupling capacitors are subjected to the high frequencies of many present applications, performance characteristics become increasingly more important. Since capacitors are fundamental to such a wide variety of applications, their precision and efficiency is imperative. Many specific aspects of capacitor design have thus been a focus for improving the performance characteristics of capacitors.
The incredible variety of capacitor environments implies that capacitors are often subjected to a number of different operating frequencies. Many wireless communications systems, including satellite, GPS, and cellular applications, as well as high speed processor applications require capacitor technology that can accommodate high frequencies of operation. Examples of capacitor technology that are designed to accommodate a generally higher frequency range of operation are disclosed in U.S. Pat. No. 6,208,501 B1 (Ingalls et al.); U.S. Pat. No. 6,023,408 (Schaper); U.S. Pat No. 5,886,867 (Chivukula et al.); U.S. Pat No. 5,576,926 (Monsorno); and U.S. Pat No. 5,220,482 (Takemura et al.). Capacitors are often designed either for such high frequency applications or for other lower frequency applications, but not both. Thus, a need exists for capacitors with diverse capabilities that are compatible with ideal operation over a wide range of frequencies. Examples of capacitors that may operate well in some limited range of frequencies can be found in U.S. Pat. No. 6,184,574 B1 (Bissey); U.S. Pat No. 6,038,122 (Bergstedt et al.); and U.S. Pat No. 5,786,978 (Mizuno).
Just as capacitors may be subjected to different frequencies of operation, so might they be subjected to different temperatures of operation. Acceptable performance at a given temperature often relates to the temperature coefficient of capacitance of the dielectric material used to form the capacitor. An existing technique that allows for desired capacitor operation at different temperatures involves stacking capacitors formed with different dielectric materials. Examples of this stacking technique can be found in U.S. Pat. Nos. 5,799,379 and 5,517,385 (Galvagni et al.).
An actual capacitor has an inherent resistance value that may not exist in a theoretical situation. This additional property of a capacitor is often referred to as equivalent series resistance (ESR). It is desired to create a capacitor that operates as close to theoretical operation as possible, and thus capacitors with low ESR are generally preferred. The need for minimal ESR is especially evident in decoupling capacitor applications. Increased ESR can increase the ripple voltage and power dissipation for a given capacitance value. This is related to the RC time constant of a capacitor and contributes to the need for low capacitor ESR. An example of a capacitor designed to offer low ESR is disclosed in U.S. Pat. No. 6,226,170 B1 (Nellison et al.).
Another way to achieve improved capacitor performance is by lowering the inductance of the device. Thus, it is preferred for decoupling capacitors to provide low equivalent series inductance (ESL) in order to maintain circuit efficiency. It may also be preferred to implement a capacitor design that reduces the self and mutual inductance of decoupling capacitors. U.S. Pat. No. 6,038,121 (Naito et al.) and U.S. Pat. No. 6,034,864 (Naito et al.) show exemplary capacitor configurations that are designed to cancel magnetic flux and reduce ESL.
Reducing the current path will lower self inductance. Since the current often has to travel the entire length of the capacitor, termination on the longer ends of the structure will reduce the current path. If the current in adjacent capacitor electrodes flows in opposite directions it will reduce the mutual inductance in a capacitor. Multiple terminations as utilized in interdigitated capacitor technology also lower the inductance value. U.S. Pat. No. 5,880,925 (DuPré et al.) and U.S. Pat No. 6,243,253 B1 (DuPré et al.) disclose multilayer capacitors that offer some of the aforementioned lower inductance characteristics. The basic configuration discussed in these DuPré patents corresponds to a type of multilayer capacitor hereafter referred to as an interdigitated capacitor (IDC).
Another approach to lowering the ESL of a decoupling capacitor is to minimize interconnect induction that results from termination configurations and mounting systems. Certain known termination schemes are characterized by high inductance and often prohibit very close spacing between components. Thus, an efficient termination scheme is desired that has low ESL and that facilitates high component density for integrated circuits. Thin film capacitor technology is used to provide exemplary capacitors for mounting on a substrate in U.S. Pat. No. 6,104,597 (Konushi) and U.S. Pat. No. 4,439,813 (Dougherty et al.).
Known termination schemes utilize electrode plates with hole arrangements therein to connect with internal columnar electrodes. Such arrangement provides a space-saving interconnect scheme with lowered ESL, but the hole arrangements in the capacitor electrodes reduce the overall capacitance of the structure by decreasing the effective area. An excess of these clearance holes can also contribute to shorting problems as the number of layers with them increases. An example of such a termination scheme can be found in European Patent Application 1,115,129 A2 (Ahiko and Ishigara.). Thus, a need exists for a termination scheme that provides low inductance-as well as high capacitance.
There are many different performance characteristics of a capacitor for which improvement may be sought to facilitate desired operation. Selected of such characteristics as mentioned and discussed above may include low ESR, low ESL and other forms of inductance, high capacitance, broad frequency range of operation, efficient termination scheme and others. Achieving many or all of these desired characteristics in a single monolithic structure would thus facilitate a beneficial capacitive structure. While various aspects and alternative features are known in the field of capacitor technology, no one design has emerged that generally integrates all of the improved performance characteristics as discussed herein.
Exemplary background references in addition to those already cited in the specification include U.S. Pat. No. 5,831,810 (Bird et al.); U.S. Pat. No. 5,811,868 (Bertin et al.); and U.S. Pat No. 5,599,757 (Wilson et al.).
The disclosures of all the foregoing United States patents are hereby fully incorporated into this application by reference thereto.